Architectures and methods for code combiners

Various embodiments are directed to systems and methods for combining a plurality of codes. The plurality of codes may be binary codes having possible logical values of -1 and +1 and may comprise an even number of codes. An output of the combining v.sub.0,k may be given by: v.sub.0=sgn(v.sub.i), where v.sub.i is the sum of the first plurality of codes at the first time. Embodiments for allocating different power levels among various codes are presented.

Patent #: 8,982,924
Author: Kumar
Issue Date: March 17, 2015
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