Developing Nanoelectronics for Space Systems
Nanoelectronic technologies offer promising capabilities. As the commercial industrial base is shifting toward their use, Aerospace is exploring how to harness the best of their features for space systems.
Gordon Moore, the cofounder of Intel, noted in a 1965 paper that the number of components in integrated circuits had doubled every year since their invention in 1958, and he predicted the trend to continue for at least ten years. Moore’s Law, as it is now known, proved accurate. In fact, the trend continued for more than half a century. Today, Moore believes this law is dead, because the doubling of the number of transistors through geometric scaling must come to an end when atomic-scale dimensions are achieved. Today’s integrated circuit transistors are fabricated in a single plane, so the lateral dimensions can shrink no smaller than the width of a few atoms or a small molecule in the best-case scenario. Commercial producers are heading toward that mark, with individual transistors having a critical dimension of ~32 nanometers (nm). Published research shows functioning transistors with channel lengths of 10 nm. For comparison, a single nucleotide in a DNA molecule is ~2.6 nm wide, and the base-pair separation is ~3.3 nm. It is reasonable to assume that in the very near future, emerging technologies will be required to continue to increase the number of active devices in an integrated circuit. Some of these nanoelectronic technologies are already being demonstrated in research laboratories, but there are no obvious best choices at this time.
Space programs may be forced to rely on nanoscale electronic devices as the commercial industrial base shifts toward these technologies. There are challenges to using these best-in-class emerging technologies, and Aerospace is investigating these technologies with an eye toward understanding how they can be harnessed for space applications.
The predominant commercial nanoscale electronic technology today is based on complementary metal-oxide semiconductor (CMOS) field-effect transistor (FET) devices using a silicon channel, high-k gate dielectric, a metal gate, and copper interconnections. This technology is used to form linear devices, switching elements, capacitors, resistors, and interconnect wiring. These basic components in turn are used to design digital logic, memory, and analog circuit functions. It is the technology used for all of the familiar “iProducts,” laptops, cellphones, and game box systems. Other electronic device technologies are in use, but nanoscale silicon CMOS logic and memory make up the vast majority of commercial production. Current space systems use earlier-generation CMOS technology in digital signal processors, solid-state recorders, flight computers, and navigation and control systems as well in communication baseband processors. Launch vehicles and ground systems use this technology to perform complementary digital processing and memory functions.
State-of-the-art space systems are using 130 nm technology and moving toward 90 nm technology. In the near term (within eight years), nanoscale CMOS will probably be the choice of space system developers, down to and including the 45 nm node. At the 32 nm node, the introduction of new materials—including gate dielectrics, gate metals, and silicon-on-insulator substrates—will signal the end of CMOS geometric scaling. Subsequent nodes, including those at 22 nm and below, are becoming increasingly difficult and costly to fabricate. The most likely solution will be technologies that expand in the third dimension by wafer stacking. In this approach, the active layer and wire interconnections of a planar circuit wafer are bonded together, and the process is repeated to stack up circuits. Metal vias provide electrical connections from one layer to the next. The subsequent assembly is then diced up and packaged in a conventional manner. DARPA has pioneered programs in 3-D integrated circuits, 3-D microsystems, and 3-D radio frequency integrated circuits. To implement these designs through silicon, vias are used with wafer bonding processes to stack the integrated circuits, one active layer upon another, and provide high-density 3-D integration.
Commercial stacked high-density memory products and 3-D integrated circuit prototype services are available today. Aside from the improvement in circuit density, 3-D stacking also provides an improvement in input/output power consumption and interconnection delays due to the tight integration of the multiple die in the wafer stack. The number of layers in a stack is limited by the total power dissipation, the mechanical complexity of repeatable alignment, and the registration required in the assembly process.
Space systems such as high-throughput digital signal processors, massively parallel processors, and solid-state data recorders would be early beneficiaries of 3-D wafer stacking. Those subsystems would have more functionality in smaller volumes with lower power than conventionally packaged planar devices with the same capability. However, certain aspects of the space environment—such as extended temperature range, thermal cycling, and radiation—may negatively affect 3-D integration and needs to be investigated (see sidebar, Design Hardening of Commercial Technologies). New technologies will still be required to continue densification after 3-D integrated circuits.
Carbon Nanotube Nanoelectronics
Carbon nanotubes are “one-dimensional” quantum materials that exhibit extraordinary material properties and striking, unique phenomena that are not found in two- or three-dimensional materials. Much of the attention given to this material has focused on its mechanical and thermal properties; composites made to exploit these properties are now being developed and used in applications (see The Next Big Thing, in this issue of Crosslink). The electronic properties of carbon nanotubes, however, are also phenomenal, perhaps even more so than the mechanical and thermal ones.
The room-temperature electron and hole mobilities in carbon nanotubes have been shown to be up to 100,000 cm2/V • sec, compared with 1400 and 8500 cm2/V • sec for silicon and gallium arsenide, respectively. Modeling studies of carbon nanotube FETs have predicted cutoff frequencies as high as 6.3 terahertz. Carbon nanotubes do not suffer from electromigration issues and can reliably carry up to 109 A/cm2, compared to 106 A/cm2 for copper, which suggests carbon nanotubes could be used for interconnections. They can be either semiconductors with diameter-tunable band gaps of 0.5–1 electron volts, or metallic, depending on the chiral wrapping angle. Carbon nanotube FETs can be made p-type or n-type simply by choosing the appropriate contact metal, allowing for the creation of dopant-free carbon-nanotube CMOS.
Several researchers have fabricated nanomechanical oscillators from carbon nanotubes, with resonant frequencies in the megahertz to gigahertz range. One group used this scheme to fabricate a complete transistor radio, with single carbon-nanotube FETs acting simultaneously as the antenna, tunable local oscillator, amplifier, and demodulator. At low temperatures, these devices exhibit single electron transistor behavior, with potential uses for infrared detection and sensitive electrometry. Because of their high surface-to-volume ratio, carbon nanotubes have the potential to make sensitive chemical sensors. Thin films of carbon nanotube networks have been used as transparent electrodes for optoelectronic applications, and carbon nanotube FETs can be fabricated on polymer substrates for use in flexible electronics.
Recent demonstrations of parallel-aligned carbon nanotube FETs have shown radio-frequency and microwave operation. These devices exploit the material and electronic properties of carbon nanotubes for the conductive channel and use a field-effect top-gate structure similar to traditional CMOS FETs. Lateral scaling continues to be limited, as in silicon CMOS, but the conductive channel is a one-dimensional quantum conductor because of the carrier confinement within the individual parallel carbon nanotubes, producing unique linearity properties. Processing of carbon nanotubes has remained one of the largest roadblocks to development, with strong efforts directed toward semiconductor-metallic carbon nanotube separation, alignment, and contact formation. Researchers are focusing on chiral-selective growth, in situ chiral-selective destruction, and chiral-selective deposition during device fabrication. Bulk purification of carbon nanotubes in solution through density ultracentrifugation and other methods has had recent success, with gram quantities of 99-percent-pure semiconductor or metallic material available for purchase commercially. These developments will open the way to mature device processing techniques.
Space system implementation of carbon nanotube FETs is now in the development stages. Novel applications are being investigated to exploit their unique quantum conduction properties. These devices will probably be hybridized with other more conventional technology, such as silicon nanoscale CMOS, where carbon nanotube FETs would be used to perform specific analog signal-processing functions. Comprehensive space environmental effects and device reliability are yet to be determined for carbon nanotube FETs, but an early study at Aerospace of gamma irradiation on carbon nanotube transistors has shown little change in device characteristics at up to 2 megarad total ionizing dose.
Carbon nanotube nanoelectronic devices were the first dimensionally confined semiconductors to be seriously investigated as replacements to silicon-based nanoelectronic FETs, and they continue to be viewed as the ultimate nanoelectronic channel for these devices. However, two significant challenges have slowed their development—making ohmic contact to carbon nanotubes, and achieving the directed growth of high-density parallel arrays of single-type semiconducting carbon nanotubes. Graphene—a single atomic layer of carbon—has been shown to be chemically stable, possess unique two-dimensionally confined electronic transport properties, and yet also allow ohmic contact; it is also compatible with conventional CMOS-like deposition and etching processes. These advantages (as well as the recognition conferred by the 2010 Nobel Prize in physics) will probably drive graphene-based nanoelectronics research for the next several years.
Perhaps the most compelling characteristics of graphene devices are that they have a symmetric drain current for positive/negative FET behavior, can be nanopatterned to form engineered band-gaps, and can conduct electrons for the distance of a micron without scattering. Together, these characteristics can enable ballistic-transport, terahertz-frequency FET operation. Electrons and holes behave as quasiparticles, called massless Dirac fermions, which are governed by the Dirac dispersion relation instead of the Schrödinger wave equation. In this mode, carriers move ballistically (scatter-free) along micron-long graphene ribbons in a manner similar to photons moving along waveguides.
IBM has recently created 100-gigahertz graphene radio frequency transistors for DARPA under its Carbon Electronics for RF Applications (CERA) program. The gate length of IBM’s graphene transistor was 240 nm. By optimizing its fabrication processes to increase mobility and reduce defects, IBM plans to increase the speed of its graphene transistors up to the CERA program goal of 1 terahertz. Although these developments have been impressive, many issues remain before they can be applied to space systems, including reliability, radiation hardness, and single-event effects behavior.
Memristor Nonvolatile Memories
Memory technologies face a similar set of challenges to CMOS logic as they are scaled to smaller dimensions. The fastest conventional memory technologies are volatile, leading to increased power consumption and a loss of stored information when the device is powered off, while nonvolatile memories often suffer from limited speed and limited lifetimes. The ideal technology would be fast and nonvolatile. Modern semiconductors of this type of nonvolatile, random-access memory (RAM) are based on flash technology, which will reach its scaling limits in the near future. Many technologies are emerging as replacement candidates, including magnetic RAM, ferroelectric RAM, phase-change-material RAM, and resistive RAM.
Resistive RAM, although behind the others in development, is very promising. This type of circuit element behaves as a memristor (a term derived from memory and resistor), a device that was predicted to exist in 1971 as the fourth circuit element (in addition to the resistor, capacitor, and inductor). Memristive devices are attractive for a number of reasons: they are nonvolatile, they have fast switching speeds, and they can be integrated into a crossbar memory structure that offers the potential to scale to very high densities.
Some of the most advanced work on resistive RAM is being conducted at Hewlett-Packard Laboratories in Palo Alto, California. The devices being developed are based on a metal/metal-oxide/metal structure, using platinum/titanium-oxide/platinum. The device is composed of two layers of titanium oxide, one that is insulating and one that is conducting. The conducting region is based on an oxygen-deficient titanium oxide that has positively charged oxygen vacancies that act to dope the material and increase its conductance. Under applied bias, these oxygen vacancies drift into the insulating region and form a conduction channel. When the bias is reversed, the oxygen vacancies are pushed back away from the electrode, destroying the conductance channel. The devices can have a high on/off ratio (up to three orders of magnitude), can switch within a few nanoseconds, and can be cycled more than 10,000 times.
Nonvolatile memories with ultimate density near 1 terabit/cm2 are predicted because the individual memristor bits are envisioned to be densely packed and addressed by nanocrossbar arrays using a 10 nm x-y pitch. The memristor bits may be incorporated heterogeneously into a conventional CMOS process, which is used to address, read, and write the memory array. Commercial devices based on this technology are currently in development and should be on the market within two years. These devices, although early in their development cycle, may provide a new high-density nonvolatile memory technology for future space systems developers. The individual memristors have been shown at Aerospace to be radiation hard to both total ionizing dose and displacement damage; however, reliability and the integration with underlying CMOS must be evaluated further before these devices can be introduced into critical space applications.
Molecular electronics—which relies on molecules to form the active (e.g., switching, sensing) or passive (e.g., rectification) elements of devices—has emerged as another possibility for post-CMOS devices. The goal is to assemble small numbers of atoms and implement them as functional circuit elements. The ability of a chemist to design functionality into a molecule is one of the advantages of molecular devices, as is their inherent scalability.
Researchers have demonstrated rectification, logic, and storage functions. Mechanically interlocked molecules, such as rotaxanes, have been used for more than a decade as the switching element in solid-state devices. A typical polymer-based molecular switch consists of a polymer backbone encircled by a ring that moves along the backbone with applied voltage into one of two stable sites. Where the ring resides will alter the electrical current in a device, resulting in a two-state (on/off) system. Molecules with the same functionality have been used to create high-density, defect-tolerant memory circuits. In 2006, a 160-kilobit molecular electronic memory with a density of 1011 bits/cm2 was demonstrated.
Significant challenges must be overcome before the implementation of useful molecular electronics—for example, the improvement of device performance and reliability. Often, the desired “molecular signature” that is seen in the solution phase does not translate into the solid state because the electrical characteristics of the electrode materials can dominate the molecule/electrode interface. Another major challenge is the realization of reproducible contacts. Often, the formation of the electrical contact can alter or damage the molecules, changing their functionality. Additionally, molecular electronic devices are often not operationally robust—a molecular memory device may degrade after just a few on/off cycles. However, improvements in synthetic techniques are providing access to a greater number of viable molecular candidates, especially ones that are being designed with robustness in mind. Once the robustness and reliability of molecular electronic devices is improved, operation in relevant space radiation environments and extended temperature ranges must be demonstrated before insertion into space systems.
Commercial markets continue to drive new nanoelectronic technology developments leading to increasing transistor density on integrated circuits. The pace and scope of this development is accelerating, and there is no shortage of future options. Carbon nanotube and graphene-based devices have the potential to reduce the lithographic challenges of straight geometric scaling while simultaneously providing FETs with superfast, room-temperature operation and ballistic charge-carrier transport. In the next decade, memristors, nanocrossbars, and self-assembled molecular electronics may provide the source materials for the next wave of nanoelectronics.
Space system developers have a great opportunity to incorporate these commercially developed technologies, using application-specific design-hardening approaches to mitigate radiation effects and life-limiting failure modes. Ideally, the gap between commercial state-of-the-art and the highest-risk nanoelectronic technology insertions should be minimized, approaching no more than a two-generation delay (~3–5 years) in the availability of a new technology for use in space applications. It is critical to maintain vigilance in studying these new developments, understanding the space-specific physics of failure, developing novel design strategies to mitigate failure modes, and reducing technical risks of first use in national security space systems.
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